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spread spectrum ftg for 440bx and via apollo pro-133 w196 preliminary cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07170 rev. *a revised december 15, 2002 features ? maximized emi suppression using cypress?s spread spectrum technology system frequency synthesizer for 440bx, 440zx, and via apollo pro-133 i 2 c programmable to 155 mhz (32 selectable frequencies) two skew-controlled copies of cpu output seven copies of pci output (synchronous w/cpu out- put) one copy of 14.31818-mhz ioapic output one copy of 48-mhz usb output selectable 24-/48-mhz clock is determined by resistor straps on power up one high-drive output buffer that produces a copy of the 14.318-mhz reference isolated core vdd pin for noise reduction key specifications supply voltages: ....................................... v ddq3 = 3.3v5% v ddq2 = 2.5v5% cpu cycle to cycle jitter: ..........................................250 ps cpu, pci output edge rate: ......................................... 1 v/ns cpu0:1 output skew: ................................................175 ps pci_f, pci1:6 output skew: .......................................500 ps cpu to pci skew: ........................ 1.5 to 4.0 ns (cpu leads) ref2x/sel48#, sclock, sdata:............... 250-k ? pull-up fs1:........................................................... 250-k ? pull-down fs0:...................................................no pull-up or pull-down note: internal pull-up or pull-down resistors should not be re- lied upon for setting i/o pins high or low. table 1. pin selectable frequency fs1 fs0 cpu(0:1) pci 1 1 133.3 mhz 33.3 mhz 1 0 105 mhz 35 mhz 0 1 100 mhz 33.3 mhz 0 0 66.8 mhz 33.3 mhz pin configuration block diagram x1 x2 gnd pci_f pci1 pci2 pci3 pci4 vddq3 pci5 pci6 vddq3 48mhz 24_48mhz/fs1 gnd ref2x/sel48# vddq3 vddq2 ioapic vddq2 cpu0 cpu1 vddq3 gnd sdata sclock fs0 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vddq3 ref2x/sel48# vddq3 ioapic cpu0 cpu1 pci_f xtal pll ref freq pll 1 fs1 x2 x1 vddq3 pci1 pci2 pci3 pci4 pci5 48mhz 24_48mhz/fs1 pll2 2/ 3 osc vddq2 pci6 gnd gnd vddq3 gnd gnd i 2 c sclock sdata logic fs0
w196 preliminary document #: 38-07170 rev. *a page 2 of 12 pin definitions pin name pin no. pin type pin description cpu0:1 22, 21 o cpu clock outputs 0 through 1: these two cpu clocks run at a frequency set by fs0:1 or the serial data interface. see table 1 and table 5 . output voltage swing is set by the voltage applied to vddq2. pci1:6 pci_f 5, 6, 7, 8, 10, 11, 4 o pci bus clock outputs 1 through 6 and pci_f: these seven pci clock outputs run synchronously to the cpu clock. voltage swing is set by the power connection to vddq3. ioapic 24 o i/o apic clock output: provides 14.318-mhz fixed frequency. the output voltage swing is set by the power connection to vddq2. 48mhz 13 o 48-mhz output: fixed 48-mhz usb clock. output voltage swing is controlled by voltage applied to vddq3. 24_48mhz/fs1 14 i/o 24-mhz or 48-mhz output/frequency select 1 input: frequency is set by the state of pin 27 on power-up. this pin doubles as the select strap to determine device operating frequency as described in table 1 . ref2x/sel48# 27 i/o i/o dual-function ref2x and sel48# pin: upon power-up, the state of sel48# is latched. the initial state is set by either a 10k resistor to gnd or to v dd . a 10k resistor to gnd causes pin 14 to output 48 mhz. if the pin is strapped to v dd , pin 14 will output 2 4mhz. after 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 mhz. fs0 16 i frequency selection 0 input: selects cpu clock frequency as shown in table 1 on page 1. sdata 18 i/o i 2 c data pin: data should be presented to this input as described in the i 2 c section of this data sheet. internal 250-k ? pull-up resistor. sclock 17 i i 2 c clock pin: the i 2 c data clock should be presented to this input as described in the i 2 c section of this data sheet. x1 1 i crystal connection or external reference frequency input: connect to either a 14.318-mhz crystal or other reference signal. x2 2 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. vddq3 9, 12, 20, 26 p power connection: power supply for core logic and pll circuitry, pci, 48/24mhz, and reference output buffers. connect to 3.3v supply. vddq2 23, 25 p power connection: power supply for ioapic and cpu output buffers. connect to 2.5v supply. gnd 3, 15, 19, 28 g ground connections: connect all ground pins to the common system ground plane.
w196 preliminary document #: 38-07170 rev. *a page 3 of 12 functional description i/o pin operation pins 14 and 27 are dual-purpose l/o pins. upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. a short time after power-up, the logic state of these pins is latched and the pins become clock outputs. this feature reduces device pin count by combining clock outputs with input select pins. an external 10-k ? ? strapping ? resistor is connected between the l/o pin and ground or v dd . connection to ground sets a latch to ? 0 ? , connection to v dd sets a latch to ? 1. ? figure 1 and figure 2 show two suggested methods for strapping resistor connections. upon w196 power-up, the first 2 ms of operation is used for input logic selection. during this period, the ref2x and 24_48mhz clock output buffers are three-stated, allowing the output strapping resistor on the l/o pin to pull the pin and its associated capacitive clock load to either a logic high or low state. at the end of the 2-ms period, the established logic ? 0 ? or ? 1 ? condition of the l/o pin is then latched. next the output buffer is enabled, which converts the l/o pin into an operating clock output. the 2-ms timer is started when v dd reaches 2.0v. the input bits can only be reset by turning v dd off and then back on again. it should be noted that the strapping resistors have no signifi- cant effect on clock output signal integrity. the drive imped- ance of the clock output is 20 ? (nominal), which is minimally affected by the 10-k ? strap to ground or v dd . as with the se- ries termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or v dd should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when the clock output is enabled following the 2-ms input pe- riod, a 14.318-mhz output frequency is delivered on the pin, assuming that v dd has stabilized. if v dd has not yet reached full value, output frequency initially may be below target but will increase to target once v dd voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. power-on reset timer output three-state data latch hold qd w196 v dd clock load 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option power-on reset timer output three-state data latch hold qd w196 v dd clock load r 10 k ? output buffer output low output strapping resistor series termination resistor jumper options resistor value r figure 2. input logic selection through jumper option
w196 preliminary document #: 38-07170 rev. *a page 4 of 12 serial data interface the w196 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. upon power-up, the w196 initializes with default register settings. therefore, the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applications, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are normally made upon system initialization, if required. the interface can also be used during system operation for power management func- tions. table 2 summarizes the control functions of the serial data interface. operation data is written to the w196 in ten bytes of eight bits each. bytes are written in the order shown in table 3 . table 2. serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock outputs to un- used pci slots. cpu clock frequency selection provides cpu/pci frequency selections beyond the selections that are provided by the fs0:1 pins. frequency is changed in a smooth and controlled fashion. for alternate microprocessors and power man- agement options. smooth frequency transition al- lows cpu frequency change under normal system operation. output three-state puts all clock outputs into a high-impedance state. production pcb testing. test mode all clock outputs toggle in relation to x1 input, in- ternal pll is bypassed. refer to table 4 . production pcb testing. (reserved) reserved function for future device revision or pro- duction device testing. no user application. register bit must be written as 0. table 3. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the w196 to accept the bits in data bytes 3 ? 6 for internal register configuration. since other devices may exist on the same com- mon serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the w196 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don ? t care unused by the w196, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial com- munication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 byte count don ? t care unused by the w196, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communi- cation protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 don ? t care refer to cypress sdram drivers. 5 data byte 1 6 data byte 2 7 data byte 3 refer to table 4 the data bits in these bytes set internal w196 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 4 , data byte serial configuration map. 8 data byte 4 9 data byte 5 10 data byte 6
w196 preliminary document #: 38-07170 rev. *a page 5 of 12 writing data bytes each bit in the data bytes control a particular device function except for the ? reserved ? bits which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 4 gives the bit formats for registers located in data bytes 3 ? 6. table 5 details additional frequency selections that are avail- able through the serial data interface. table 6 details the select functions for byte 3, bits 1 and 0. note: 1. bits 0 and 1 of data byte 6 in table 4 must be programmed as the same value. table 4. data bytes 3 ? 6 serial configuration map bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 3 7 -- -- sel_3 refer to table 5 0 6 -- -- sel_2 refer to table 5 0 5 -- -- sel_1 refer to table 5 0 4 -- -- sel_0 refer to table 5 0 3 -- -- frequency table selection frequency controlled by external fs0:1 pins ( table 1 ) frequency controlled by byt3 sel_(3:0) table 5 0 2 -- -- (reserved) -- -- 0 1 ? 0 -- -- bit 1 bit 0 function (see table 6 for function details) 0 0 spread spectrum off 0 1 test mode 1 0 spread spectrum on (default) 1 1 all outputs three-stated 10 data byte 4 7 -- -- (reserved) -- -- 0 6 14 24/48mhz clock output disable low active 1 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 21 cpu1 clock output disable low active 1 1 -- -- (reserved) -- -- 0 0 22 cpu0 clock output disable low active 1 data byte 5 7 4 pci_f clock output disable low active 1 6 11 pci6 clock output disable low active 1 5 10 pci5 clock output disable low active 1 4 - -- (reserved) -- -- 0 3 8 pci4 clock output disable low active 1 2 7 pci3 clock output disable low active 1 1 6 pci2 clock output disable low active 1 0 5 pci1 clock output disable low active 1 data byte 6 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 24 ioapic clock output disable low active 1 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 27 ref2x clock output disable low active 1 [1] 0 27 ref2x clock output disable low active 1 [1]
w196 preliminary document #: 38-07170 rev. *a page 6 of 12 note: 2. cpu and pci frequency selections are listed in ta ble 1 and tab le 5 . table 5. additional frequency selections through serial data interface data bytes input conditions data byte 3, bit [7:4, 1:0] output frequency if spread is on bit [1:0] bit 7 sel_3 bit 6 sel_2 bit 5 sel_1 bit 4 sel_0 cpu, sdram clocks (mhz) pci clocks (mhz) spread percentage 00 0 0 0 0 78 39 off 00 0 0 0 1 81 40.5 off 00 0 0 1 0 113.5 37.8 off 00 0 0 1 1 66.8 33.4 off 00 0 1 0 0 117 39 off 00 0 1 0 1 118.5 39.5 off 00 0 1 1 0 122 37.3 off 00 0 1 1 1 100 33.3 off 00 1 0 0 0 126 31.5 off 00 1 0 0 1 135 33.75 off 00 1 0 1 0 137 34.25 off 00 1 0 1 1 138.5 34.62 off 00 1 1 0 0 142 35.5 off 00 1 1 0 1 144 36 off 00 1 1 1 0 155 38.75 off 00 1 1 1 1 133.3 33.3 off 10 0 0 0 0 124 41.3 0.5% center 10 0 0 0 1 75 37.5 0.5% center 10 0 0 1 0 83.3 41.65 0.5% center 10 0 0 1 1 66.8 33.4 0.5% center 10 0 1 0 0 90 30 0.5% center 10 0 1 0 1 112 37.3 0.5% center 10 0 1 1 0 95 31.67 0.5% center 10 0 1 1 1 100 33.3 0.5% center 10 1 0 0 0 120 40 0.5% center 10 1 0 0 1 115 38.3 0.5% center 10 1 0 1 0 110 36.67 0.5% center 10 1 0 1 1 105 35 0.5% center 10 1 1 0 0 140 35 0.5% center 10 1 1 0 1 150 37.5 0.5% center 10 1 1 1 0 124 31 0.5% center 10 1 1 1 1 133.3 33.3 0.5% center table 6. select function for data byte 3, bits 0:1 function input conditions output conditions data byte 3 cpu0:1 pci_f, pci1:6 ref2x, ioapic 48mhz 24mhz bit 1 bit 0 spread spectrum off 0 0 note 2 note 2 14.318 mhz 48 mhz 24 mhz test mode 0 1 x1/2 cpu/2, 3, or 4 x1 x1/2 x1/4 spread spectrum on (default) 1 0 0.5% 0.5% 14.318 mhz 48 mhz 24 mhz three-state 1 1 hi-z hi-z hi-z hi-z hi-z
w196 preliminary document #: 38-07170 rev. *a page 7 of 12 absolute maximum ratings [3] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c esd prot input esd protection 2 (min.) kv dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit supply current i ddq3 combined 3.3v supply current cpu0:1 =100 mhz outputs loaded [4] 85 ma i ddq3 combined 2.5v supply current cpu0:1 =100 mhz outputs loaded [4] 30 ma logic inputs v il input low voltage gnd ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input low current [5] ? 25 a i ih input high current [5] 10 a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v v oh output high voltage cpu0:1/ioapic i oh = ? 1 ma 2.2 v i ol output low current cpu0:1 v ol = 1.25v 45 60 80 ma pci_f, pci1:6 v ol = 1.5v 85 110 140 ma ioapic v ol = 1.25v 65 90 140 ma ref2x v ol = 1.5v 110 140 170 ma 48mhz, 24mhz v ol = 1.5v 50 70 90 ma i oh output high current cpu0:1 v ol = 1.25v 35 50 80 ma pci_f, pci1:6 v ol = 1.5v 60 95 130 ma ioapic v ol = 1.25v 45 87 140 ma ref2x v ol = 1.5v 100 130 150 ma 48mhz, 24mhz v ol = 1.5v 50 70 90 ma crystal oscillator v th x1 input threshold voltage [6] v ddq3 = 3.3v 1.65 v c load load capacitance, as seen by external crystal [7] 14 pf c in,x1 x1 input capacitance [8] pin x2 unconnected 28 pf notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required 4. all clock outputs loaded with maximum lump capacitance test load specified in the ac electrical characteristics section. 5. w196 logic inputs have internal pull-up resistors, except sel100/66# (pull-ups not full cmos level). 6. x1 input threshold voltage (typical) is v dd /2. 7. the w196 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total l oad placed on crystal is 14 pf; this includes typical stray capacitance of short pcb traces to crystal. 8. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected).
w196 preliminary document #: 38-07170 rev. *a page 8 of 12 ac electrical characteristics t a = 0 c to +70 c, v ddq3 = 3.3v5%,v ddq2 = 2.5v 5%, f xtl = 14.31818 mhz ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; spread spectrum clocking is disabled. pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6pf l in input pin inductance 7nh dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% (continued) parameter description test condition min. typ. max. unit cpu clock outputs, cpu0:1 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.8 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.25v 15 15.5 10 10.5 ns t h high time duration of clock cycle above 2.0v 5.2 3.0 ns t l low time duration of clock cycle below 0.4v 5.0 2.8 ns t r output rise edge rate measured from 0.4v to 2.0v 1 4 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.25v. max- imum difference of cycle time between two adjacent cycles. 200 250 ps t sk output skew measured on rising edge at 1.25v 175 175 ps f st frequency stabiliza- tion from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transi- tion. used for determining series termi- nation value. 20 20 ?
w196 preliminary document #: 38-07170 rev. *a page 9 of 12 pci clock outputs, pci1:6 and pci_f (lump capacitance test load = 30 pf parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 500 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 14ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 20 ? ioapic clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate measured from 0.4v to 2.0v 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? ref2x clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ?
w196 preliminary document #: 38-07170 rev. *a page 10 of 12 48-mhz and 24-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments min. typ. max. unit f frequency, actual determined by pll divider ratio (see m/n below) 48.008 24.004 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17, 57/34 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ? ordering information ordering code package name package type w196 g 28-pin soic (300 mils)
w196 preliminary document #: 38-07170 rev. *a page 11 of 12 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 28-pin small outline integrated circuit (soic, 300 mils)
w196 preliminary document #: 38-07170 rev. *a page 12 of 12 document title: w196 spread spectrum ftg for 440bx and via apollo pro-133 document number: 38-07170 rev. ecn no. issue date orig. of change description of change ** 110280 11/05/01 szv change from spec number: 38-00842 to 38-07170 *a 122811 12/15/02 rbi add power up requirements to maximum ratings information

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